Implantable stimulation devices are devices that generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability in any implantable medical device system, including a Deep Brain Stimulation (DBS) system.
As shown in FIGS. 1A-1C, an SCS system typically includes an Implantable Pulse Generator (IPG) 10 (Implantable Medical Device (IMD) 10 more generally), which includes a biocompatible device case 12 formed of a conductive material such as titanium for example. The case 12 typically holds the circuitry and power source (e.g., battery) 14 (FIG. 1C) necessary for the IPG 10 to function, although IPGs can also be powered via external RF energy and without a battery. The IPG 10 is coupled to electrodes 16 via one or more electrode leads 18, such that the electrodes 16 form an electrode array 20. The electrodes 16 are carried on a flexible body 22, which also houses the individual signal wires 24 coupled to each electrode. In the illustrated embodiment, there are eight electrodes (Ex) on two leads 18 for a total of sixteen electrodes 16, although the number of leads and electrodes is application specific and therefore can vary. The leads 18 couple to the IPG 10 using lead connectors 26, which are fixed in a non-conductive header material 28, which can comprise an epoxy for example.
As shown in the cross-section of FIG. 1C, the IPG 10 typically includes a printed circuit board (PCB) 30, along with various electronic components 32 mounted to the PCB 30, some of which are discussed subsequently. Two coils (more generally, antennas) are shown in the IPG 10: a telemetry coil 34 used to transmit/receive data to/from an external controller (not shown); and a charging coil 36 for charging or recharging the IPG's battery 14 using an external charger (not shown). FIG. 1B shows these aspects in perspective with the case 12 removed for easier viewing. Telemetry coil 34 may alternatively comprise a short range RF antenna for wirelessly communicating in accordance with a short-range RF standard such as Bluetooth, WiFi, MICS, Zigbee, etc., as described in U.S. Patent Application Publication 2016/0051825.
FIGS. 2A and 2B show an architecture 140 for the circuitry in IPG 10, which is disclosed in U.S. Provisional Patent Application Ser. Nos. 62/386,000 and 62/393,003, filed Sep. 10, 2016, which are incorporated by reference in their entireties. Architecture 140 includes at least one Application Specific Integrated Circuit (ASIC) 160. ASIC 160 includes a microcontroller block 150, which as shown in FIG. 2B can communicate with other functional blocks in the ASIC 160 via internal bus 192. Because ASIC 160 includes an internal microcontroller 150, an external microcontroller can be dispensed with in the improved architecture 140, simplifying IPG design and saving room within the interior of the case 12 and on the IPG's PCB 30 (FIG. 1C). In one example, the microcontroller block 150 can comprise circuitry from an ARM Cortex-M0+ Processor, which may be incorporated into the monolithic integrated circuit of the ASIC 160 by licensing various necessary circuits from the library that comprises that processor. ASIC 160 can comprise a monolithic integrated circuit formed on its own semiconductive substrates (“chip”), and may be contained in its own package and mounted to the IPG 10's PCB 30.
Microcontroller block 150 may receive interrupts independent of the bus 192 and its communication protocol, although interrupts may also be sent to the microcontroller block 150 via the bus 192 as well. Even though ASIC 160 includes a microcontroller block 150, the ASIC 160 may still couple to an external bus 190. This can facilitate communications between the ASIC 160 and another device, such as a memory integrated circuit (not shown) or possibly another microcontroller device that might be coupled to the bus 190 as explained in the above-incorporated '000 and '003 Applications. Bus 190 can also facilitate communication between (master) ASIC 160 and another identically-constructed (slave) ASIC 160′, shown in dotted lines in FIG. 2A. Use of an additional ASIC 160′ allows the number of electrodes 16 the IPG 10 supports to be doubled, for example from sixteen to thirty two, or thirty two to sixty four. Off-bus connections 54 can facilitate master/slave interaction between ASICs 160 and 160′, and as explained in detail in the above-incorporated '000 and '003 Applications.
FIG. 2B shows various functional circuit blocks within ASIC 160, which are briefly described. As mentioned, ASIC 160 includes an internal bus 192 which can couple to external bus 190 and which may duplicate bus 190's signals. Note that each of the functional blocks includes interface circuitry 88 enabling communication on the internal bus 192. Interface circuitry 88 helps each block recognize when microcontroller block 150 is communicating data with addresses pertaining to that block via bus 192.
ASIC 160 contains several terminals 61 (e.g., pins, bond pads, solder bumps, etc.), such as those necessary to connect to the external bus 190, the battery 14, the coils 34, 36, external memory (not shown), etc. ASIC terminals 61 include electrode nodes 61a (E1′-E16′ and Ec′) which circuit nodes are also present on the PCB 30 (FIG. 1C) inside of the IPG's case 12. The electrode nodes 61a connect to the electrodes 16 (E1-E16) on the lead(s) 18 outside of the case 12 by way of DC-blocking capacitors 55. As is known, DC-blocking capacitors 55 are useful to ensure that DC current isn't inadvertently (e.g., in the event of failure of the ASIC 160's circuitry) injected into the patient's tissue, and hence provide safety to the IPG 10. Such DC-blocking capacitors 55 can be located on or in the IPG 10's PCB 30. See U.S. Patent Application Publication 2015/0157861. Note that there is also an electrode node 61a Ec′ which is connected to the case (preferably by a DC-blocking capacitor 55), thus allowing the case 12 to operate as an electrode 16 (Ec). ASIC 160 may support other numbers or types of electrode nodes/electrodes (e.g., thirty-two electrodes E1-E32 plus the case Ec).
Each of the circuit blocks in ASIC 160 performs various functions in IPG 10. Telemetry block 64 couples to the IPG telemetry coil 34, and includes transceiver circuitry for wirelessly communicating with an external device according to a telemetry protocol. Such protocol may comprise Frequency Shift Keying (FSK), Amplitude Shift Keying (ASK), or various short-range RF standards such as those mentioned above. Charging/protection block 62 couples to the IPG charging coil 38, and contains circuitry for rectifying power wirelessly received from an external charger (not shown), and for charging the battery 14 in a controlled fashion.
Analog-to-Digital (A/D) block 66 digitizes various analog signals for interpretation by the IPG 10, such as the battery voltage Vbat or voltages appearing at the electrodes, and is coupled to an analog bus 67 containing such voltages. A/D block 66 may further receive signals from sample and hold block 68, which can be used to measure such voltages, or differences between two voltages. For example, sample and hold circuitry 68 may receive voltages from two electrodes and provide a difference between them (see, e.g., VE1-VE2 in FIG. 3, discussed subsequently), which difference voltage may then be digitized at A/D block 66. Knowing the difference in voltage between two electrodes when they pass a constant current allows for a determination of the (tissue) resistance between them, which is useful for a variety of reasons.
Sample and hold block 68 may also be used to determine one or more voltage drops across the DAC circuitry 172 (see Vp and Vn in FIG. 3, explained subsequently) used to create the stimulation pulses. This is useful to setting the compliance voltage VH to be output by a compliance voltage generator block 76. Compliance voltage VH powers the DAC circuitry 172, and the measured voltage drops can be used to ensure that the compliance voltage VH produced is optimal for the stimulation current to be provided—i.e., VH is not too low to be unable to produce the current required for the stimulation, nor too high so as to waste power in the IPG 10. Measuring Vp and Vn to determine whether VH is too high or too low is particularly useful because the resistance Rt of the patient's tissue may not be known in advance, or may change over time. Thus, the voltage drop across the tissue, Vrt, may change as well, and monitoring Vp and Vn provides an indication of such changes, and hence whether VH should be adjusted. Compliance voltage generator block 76 includes circuitry for boosting a power supply voltage such as the battery voltage, Vbat, to a proper level for VH. Such boost circuitry (some of which may be located off chip) can include an inductor-based boost converter or a capacitor-based charge pump, which are described in detail in U.S. Patent Application Publication 2010/0211132.
Clock generation block 74 can be used to generate a clock for the ASIC 160 and communication on the bus 192. Clock generation block 74 may receive an oscillating signal from an off-chip crystal oscillator 56, or may comprise other forms of clock circuitry located completely on chip, such as a ring oscillator. U.S. Patent Application Publication 2014/0266375 discloses another on-chip circuit that can be used to generate a clock signal on the ASIC 160.
Master/slave control block 86 can be used to inform the ASIC 160 whether it is to be used as a master ASIC or as a slave ASIC (e.g., 160 or 160′ in FIG. 2A), which may be bond programmed at M/S terminal 61. For example, M/S terminal may be connected to a power supply voltage (e.g., Vbat) to inform ASIC 160 that it will operate as a master ASIC, or to ground to inform that it will operate as a slave 160′, in which case certain function blocks will be disabled, as the above-cited references explain.
Nonvolatile memory (NOVO) block 78 caches any relevant data in the system (such as log data). Additional memory (not shown) can also be provided off-chip via a serial interface block 84.
ASIC 160 further includes a stimulation circuitry block 170, which includes circuitry for receiving and storing stimulation parameters from the microcontroller block 150 via bus 192. Stimulation parameters define the shape and timing of stimulation pulses to be formed at the electrodes, and can include parameters such as which electrodes E1-E16 will be active; whether those active electrodes are to act as anodes that source current to a patient's tissue, or cathodes that sink current from the tissue; and the amplitude (A), duration (D), and frequency (f) of the pulses. Amplitude may comprise a voltage or current amplitude. Such stimulation parameters may be stored in registers in the stimulation circuitry block 170. See, e.g., U.S. Patent Application Publications 2013/0289661; 2013/0184794.
Simulation circuitry block 170 also includes a Digital-to-Analog Converter (DAC) 172 for receiving the stimulation parameters from the registers and for forming the prescribed pulses at the selected electrodes. FIG. 3 shows a simple example of DAC circuitry 172 as used to provide a current pulse between selected electrodes E1 and E2 and through a patient's tissue, Rt. DAC circuitry 172 as shown comprises two portions, denoted as PDAC 172p and NDAC 172n. These portions of DAC circuitry 172 are so named because of the polarity of the transistors used to build them and the polarity of the currents they provide. Thus, PDAC 172p is formed from P-channel transistors and is used to source a current +I to the patient's tissue Rt via a selected electrode E1 operating as an anode. NDAC 172n is formed of N-channel transistors and is used to sink current −I from the patient's tissue via a selected electrode E2. It is important that current sourced to the tissue at any given time equal that sunk from the tissue to prevent charge from building in the tissue, although more than one anode electrode and more than one cathode electrode may be operable at a given time.
PDAC 172p and NDAC 172n receive digital control signals from the registers in the stimulation circuitry block 170, denoted <Pstim> and <Nstim> respectively, to generate the prescribed pulses with the prescribed timing. In the example shown, PDAC 172p and NDAC 172n comprise current sources, and in particular include current-mirrored transistors for mirroring (amplifying) a reference current Iref to produce pulses with an amplitude, A. PDAC 172p and NDAC 172n could however also comprise constant voltage sources. Control signals <Pstim> and <Nstim> also prescribe the timing of the pulses, including their duration (D) and frequency (f), as shown in the waveforms generated at the selected electrodes. The PDAC 172p and NDAC 172n along with the intervening tissue Rt complete a circuit between a power supply VH—the compliance voltage as already introduced—and ground. As noted earlier, the compliance voltage VH is adjustable to an optimal level at compliance voltage generator block 76 (FIG. 2B) to ensure that current pulses of a prescribed amplitude can be produced without unnecessarily wasting IPG power.
The DAC circuitry 172 (PDAC 172p and NDAC 172n) may be dedicated at each of the electrodes, and thus may be activated only when its associated electrode is selected as an anode or cathode. See, e.g., U.S. Pat. No. 6,181,969. Alternatively, the current produced by one or more DACs (or one or more current sources within a DAC) may be distributed to a selected electrode by a switch matrix (not shown), in which case optional control signals <Psel> and <Nsel> would be used to control the switch matrix and establish the connection between the selected electrode and the PDAC 172p or NDAC 172n. See, e.g., U.S. Pat. No. 8,606,362. DAC circuitry 172 may also use a combination of these dedicated and distributed approaches. See, e.g., U.S. Pat. No. 8,620,436.
In the example waveform shown, the pulses provided at the electrodes are biphasic, meaning that each pulse comprises a first phase 94a of a first polarity, followed by a second phase 94b of an opposite polarity. This is useful as a means of active recovery of charge that may build up on the DC-blocking capacitors 55. Thus, while charge will build up on the capacitors 55 during the first pulse phase 94a, the second pulse phase 94b will actively recover that charge, particularly if the total amount of charge is equal in each phase (i.e., of the area under the first and second pulse phases are equal). Recovery of excess charge on the DC-blocking capacitors 55 is important to ensure that the DAC circuitry 172 will operate as intended: if the charge/voltage across the DC-blocking capacitors 55 is not zero at the end of each pulse, remaining charge/voltage will skew formation of subsequent pulses, which may therefore not provide the prescribed amplitude.
While active recovery of charge using a biphasic pulse is beneficial, such active recovery may not be perfect, and hence some residual charge may remain on the DC-blocking capacitors 55 even after completion of the second phase 94b of the biphasic pulse. Thus, the art has recognized the utility of passive charge recovery. Passive charge recovery is implemented within the stimulation circuitry block 170, and includes use of passive recovery switches (transistors) 96, which are connected between the electrode nodes (E1′-E16′) 61a and a common reference voltage. This voltage as shown may simply comprise the battery voltage, Vbat, but another reference voltage could also be used. Closing the passive recovery switches 96 during a time period 98 after the second pulse phase 94b couples the DC-blocking capacitors 55 in parallel between the reference voltage and the patient's tissue, Rt. Given the previous serial connection of the DC-blocking capacitors 55, this should normalize any remaining charge. See e.g., U.S. Provisional Patent Application Ser. No. 62/393,007, filed Sep. 10, 2016 (discussing advents related to passive recovery).